There is an increasing demand for electrically programmable and erasable nonvolatile semiconductor memory devices NAND type FLASH memory devices are memory devices capable of storing a large amount of data. These high-integration devices substantially comprise a plurality of memory cells connected in series to form a plurality of series of cells that form a memory array of cells.
Each cell has a current path between respective source and drain regions of the cell formed in a semiconductor substrate. A floating gate functionally overhangs the channel region between the source and drain regions, and a control gate is capacitively coupled to the floating gate.
FLASH memory cells are programmed by connecting a source region of the cell and the semiconductor substrate, i.e., a bulk region, to a node at ground potential, and applying a relatively high voltage (program voltage) ranging for example from 15V to 20V to the control gate. Also, a voltage ranging for example from 5 to 6V is applied to the drain of the memory cell to generate hot charge carriers. The hot charge carriers supplied by the drain region (electrons) are gathered and accumulated in the floating gate because of the intense electric field created by the high voltage applied to the control gate.
The erase operation for programmed FLASH memory cells is performed simultaneously on all the programmed cells of a certain sector of the whole array of cells. The same bulk region is shared, and the erase operation comprises applying a relatively high negative voltage (erase voltage) for example −10V to the control gate. A positive voltage for example 5V is applied to the bulk region to determine conditions for the Fowler-Nordheim (F-N) tunneling effect that causes the electrons accumulated on the floating gate of a programmed cell to discharge toward the source region. The erase threshold voltage of present FLASH memory cells typically ranges from 1V to 3V.
In general, the above described program or erase operations are repeated a plurality of times on a same cell for progressively charging or discharging its floating gate, respectively. At each step, the state of the cell is verified and a further program or erase step is carried out or not depending on whether the cell is correctly programmed or erased.
The memory cell, the threshold voltage of which was increased by one or a succession of program steps, is nonconductive (OFF) because current is prevented from flowing from the drain region to the source region. The memory cell, the threshold voltage of which was lowered by one or a succession of erase steps is conductive (ON) because current may flow from the drain region to the source region.
Typically, in FLASH memory devices the whole storage space is organized in pages. Each page substantially comprises an array (or sub-array) of addressable cells. Such an organization and the presence of a buffer page register allows all the cells of a page to be programmed or erased simultaneously.
Each page has a respective bank of redundancy cells for substituting cells found to be defective in an EWS testing phase of the memory device being fabricated. During this testing phase fuses are burned for redirecting the address of a memory location containing a failed cell to a certain redundancy column of cells, thus substituting the column of cells containing failed cells.
A Copyback Program in nonvolatile memory devices is an important function for quickly and efficiently rewriting data stored in a page (source page) to another page (destination page). An internal buffer register is used for temporarily storing data read from the source page.
The general procedure of a Copyback Program is shown in FIG. 1 and includes the following operations.
1) Data is read from a Source Page and is stored in an internal register;
2) Data stored in the internal register is programmed into a destination page, and a Program-Verify operation is carried out; and
3) A Pass/Fail check is performed In case of a fail, step 2) is carried out again, otherwise the Copyback Program is finished.
In the ensuing description reference is made to NAND FLASH memory devices, though the same considerations hold for any kind of nonvolatile memory device that contemplates a Copyback Program operation, such as a NOR FLASH memory, etc.
A sample timing diagram of the main signals of a NAND FLASH memory during a Copyback Program operation is depicted in FIG. 2. The meaning of each label is provided in TABLE 1:
TABLE 1CLECommand Latch Enable CEChip Enable WEWrite EnableALEAddress Latch Enable RERead EnableI/O0-7Data Input/OutputsR/ BReady/BusytWCWrite Cycle TimetWB WE High to BusytRData Transfer from Cell to registertPROGProgram Time
As shown in FIG. 2, a Copyback Program operation is a sequence of Page-Read operations at the Source Page Address and Copying Program operations at the Destination Page Address. After the Copying Program operation is completed, the Program Verify operation is carried out, and a pass/fail flag is generated for signaling whether the Copyback Program operation is successfully completed or not.
If the Destination Page has a cell that needs higher programming voltages to be programmed than the other cells, a fail may be flagged in the first programming attempt. In this case, the program operation is performed again by increasing the programming voltage.
There are two operations of cell verification in nonvolatile memory devices: 1) Global Verify operation; and 2) Byte-by-byte Verify operation. Global Verify operation is a very fast method for verifying programmed cells. To better understand how it works, reference is directed to FIG. 3 illustrating a NAND memory with a page buffer. The meaning of each label is provided in TABLE 2.
TABLE 2DSLDrain Select LineWLWordlineSSLSource Select LineBLeoutput of an even bitlineBLooutput of an odd bitlineVIRPWRVirtual powerDISCHecontrol signal for discharging the outputof the even bitlineDISCHocontrol signal for discharging the outputof the odd bitlineBSLeselection signal of the even bitlineBSLoselection signal of the odd bitlinePRECH_Npre-charge signalSOsense outPGMprogram control signalQBlatched data stored in the selected cellPBDOpage buffer data output control signalMLCHmain latch signalMRSTreset signalnWDObitline fail flag
If a 0 is to be stored in the selected cell (programmed cell), the latched datum QB is 0. When verifying the cell, if the selected cell results in being programmed (0), the cell is in an off state, the signal BLe is logically active. Therefore, the latched datum QB becomes logically active when a pulse MLCH is generated. In this situation, the bitline fail flag nWDO remains floating.
If a 1 is to be stored in the selected cell (erased cell), the latched datum QB is 1. When verifying the cell, if the selected cell results in being erased, the cell is in an on state. The signal BLe is logically active and QB remains logically active (1). Also in this case, the bitline fail flag nWDO remains floating.
A general pass/fail flag of the Global Verify operation is generated by the circuit of FIG. 4 that logically combines all the bitline pass/fail flags corresponding to the nWDO signals If all the cells selected for storing a 0 are programmed successfully, all nWDO signals will be floating. Thus, when the logic signal CHECK switches active, the global pass/fail flag PASS assumes a high logic value.
Otherwise, if a cell selected to be programmed remains conductive (erased), then the BLe signal is logically null. Therefore, when the MLCH pulse is generated, the latched datum QB remains null and the nWDO flag is logically high. If at least one flag nWDO is high, the global pass/fail flag PASS is low, signaling that the global program operation has failed. In a Global Verify operation all nWDO flags are combined together simultaneously for generating a global pass/fail flag.
The other verification operation is the Byte-by-byte Verify (or Word-by-word Verify in a 16× mode) is an accurate but relatively long operation because the cells are verified Byte-by-byte (or Word-by-word) by sequentially incrementing the column address in the corresponding page. The Byte-by-byte Verify operation starts with the first column address and is repeated for all column addresses up to the last column address. Generally, the Byte-by-byte Verify operation is used only for verifying erased cells and is carried out by dedicated Erase-Verify circuits included in every NAND memory device.
A typical scheme of a NAND memory with a page buffer and with redundancy redirect is depicted in FIG. 5. A pass-gate controlled by the signal YA/YB transfers the latched datum to a multiplexer of a bank of multiplexers when the grounding command DL_DIS is null.
As depicted in FIG. 6, each multiplexer is input with signals DL corresponding to latched data, and with corresponding signals generated by a bitline of a redundancy register corresponding to the addressed bitline. Each multiplexer generates a bitline pass/fail flag DL_O as a replica of a signal DL or of its corresponding signal generated by a redundancy bitline depending on whether redundancy is enabled or not.
The circuit of FIG. 7 generates a global pass/fail flag E_PASSFAIL by logically combining all bitline pass/fail flags DL_O. When verifying the selected cell, the latch, highlighted by a surrounding dash-line perimeter, transfers DL0 to a PASS/FAIL check circuit. The PASS/FAIL check circuit evaluates each DL_O signals by byte (or word). Therefore, it is possible to verify only one byte (or word) at the time. To verify the next byte (or word), the column address is again sequentially incremented until the last column address of the byte (or word) is reached.
The Byte-by-byte Verify operation takes a long time if it is carried out on the whole memory, but provides an accurate verification of the state of the cells Generally, it is not possible to employ the Byte-by-byte Verify operation for Program Verify because of strict timing specifications that are commonly imposed for performing a pre-established maximum number of Program Verify operations.
For example, suppose that the maximum program time in conventional NAND FLASH memory specification is 700 μs, and the maximum number of program attempts is 12. When executing the Global Verify operation after each attempt, the maximum program time for 12 attempts is about 620 μs. This comfortably meets the specifications.
Should a Byte-by-byte Verify operation be performed instead of a Global Verify operation after each attempt, the program time for 12 attempts would be about 1200 μs. This is well beyond the maximum time allowed by the specifications This explains why Byte-by-byte Verify is not adopted for carrying out Program Verify operations, and why a Global Verify operation is normally used.
For various reasons, there may be defective cells in a finished memory device. A defective cell can be a short-type defective cell or an open-type defective cell. In a short-type defective cell, the datum stored therein is always 1. That is, the cell always results as an erased cell and cannot be programmed. In an open-type defective cell, the stored datum is always 0. That is, the cell is always seen as a programmed cell and cannot be erased.
An example of an open-type defective cell is a cell in which the drain region is disconnected. A short-type defective cell may be a cell affected by an excessive leakage, or its drain region is shorted to ground.
Finished NAND FLASH memory devices are tested once more and are either marked as good or discarded depending on the test results. Generally, memory devices are discarded if they need more than a certain number M of program attempts to be correctly programmed.
When the Program-Verify operation is carried out in a Copyback Program mode, sometimes the global pass/fail flag PASS always signals a fail. This is notwithstanding the fact that the programmed cells in the destination page pass a Read test.
It has been statistically determined that this inconvenience occurs when the Copyback Program operation is executed from an odd to an even page, or vice versa. For this reason, certain manufacturers enable the Copyback Program operation only from an odd to an odd page or from an even to an even page. This type of safeguard significantly limits the way the whole memory space can be exploited.